Si channel surface dependence of electrical characteristics in ultra-thin gate oxide CMOS

Introduction For high-speed logic applications, suppression of the power consumption is very important and thus supply voltage should be reduced at every new generation. In order to realize high performance despite a low supply voltage, gate oxide thickness has to be reduced continuously. In fact, it has been suggested that even 1.6 -1.1 nm EOT (equivalent physical SiO2 thickness) gate insulator be used for 45 nm gate length MOSFETs in 100-nm technology node [1]. With thinning the gate oxides, the quality control of Si/insulator interface would dominate performance and reliability. It is also pointed out that high-k gate devices in future use would need interfacial layer between Si and high-k insulator in order to realize high quality of interface [2]. This paper reviews recent work concerning Si/ SiO2 interface quality of MOSFETs, such as various Si surface channel orientations [3,4] and epitaxitial Si channel layer [5].